Analog to Digital Converters (ADCs) are used to generate a sequence of digital codes representing the strength of an input signal at corresponding time instants. A pipeline ADC is a type of ADC which contains a sequence of (pipeline) stages, with each stage resolving a number of bits forming a sub-code. The sub-codes generated by various stages are used to generate a digital code corresponding to the analog input sampled by the ADC.
A sub-ADC generally refers to an ADC component (contained in a stage of a ‘ADC’ noted in the above paragraph) that generates a coarse (low-resolution) digital equivalent (sub-code noted above) of the corresponding input to the stage. Each stage (except the last stage) of a pipeline ADC generates a residue signal which is the difference of the input signal and the analog equivalent of the sub-code, the residual signal representing that portion of the input signal that needs to be resolved by subsequent stages. The residue signal represents a difference of the voltage of the input signal to the stage and the voltage value corresponding to the sub-code provided by the stage. The residue signal (in an amplified form, typically) of one stage is provided as an input signal to the next stage in the sequence.
A sub-ADC in a pipeline ADC may be associated with various errors. An offset error is generally present when an operational parameter (affecting the values of the digital codes generated) deviates in an ADC from a corresponding desired value. For example, while it may be desirable that different sub-components of a stage of a pipeline ADC sample the input signal to that stage at a same/identical time instants, the components may not sample the input signal at the same time instant.
Thus, a sub-ADC may sample an input signal at time instants which are offset (different) from the (corresponding) instants at which other components of the stage sample the same input signal. The difference of sampling instants represents a timing offset (also termed sampling mismatch) error. Similarly, it may be desirable that voltage thresholds (the voltage value at which the equivalent digital value changes to a next value) used in a flash ADC of a stage not deviate from desired values, a deviation being termed a voltage offset error.
Such offset errors generally cause corresponding errors in the output digital codes of a pipeline ADC. It is accordingly desirable that offset errors be corrected such that the digital codes accurately represent the strength of an input signal at the sampled time instant.
Several aspects of the present invention correct for offset errors associated with one or more sub-ADCs in a pipeline ADC.